Single-ended subthreshold SRAM with asymmetrical write/read-assist

Ming Hsien Tu; Jihi Yu Lin; Ming Chien Tsai; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/TCSI.2010.2071690

Single-ended subthreshold SRAM with asymmetrical write/read-assist

Ming Hsien Tu^*, Jihi Yu Lin, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

121 Scopus citations

Abstract

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V_DD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

Original language	English
Article number	5634142
Pages (from-to)	3039-3047
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	57
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2010.2071690
State	Published - 2010

Keywords

Low power
low voltage
single-ended SRAM

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10.1109/TCSI.2010.2071690

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abstract = "In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.",

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AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

PY - 2010

Y1 - 2010

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AB - In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V VDD, an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

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KW - low voltage

KW - single-ended SRAM

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ER -

Single-ended subthreshold SRAM with asymmetrical write/read-assist

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Keywords

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