Simultaneous Switching Noise analysis and low bouncing buffer design

Shyh-Jye Jou; Wei Chung Cheng; Yu Tao Lin

doi:10.1109/CICC.1998.695037

Simultaneous Switching Noise analysis and low bouncing buffer design

Shyh-Jye Jou^*, Wei Chung Cheng, Yu Tao Lin

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

12 Scopus citations

Abstract

An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

Original language	English
Pages (from-to)	545-548
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1998.695037
State	Published - 1 Jan 1998
Event	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 11 May 1998 → 14 May 1998

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10.1109/CICC.1998.695037

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abstract = "An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.",

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N2 - An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

AB - An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

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M3 - Conference article

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JF - Proceedings of the Custom Integrated Circuits Conference

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Simultaneous Switching Noise analysis and low bouncing buffer design

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