Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture

Keyphrases

• Data Transfer 100%
• Communication Architecture 100%
• Multicycle Communication 100%
• Wire Delay 66%
• Distributed-register Architecture 66%
• System Performance 33%
• Scheduler 33%
• Router 33%
• Deep Submicron Technology 33%
• Temporal Domain 33%
• Channel Allocation 33%
• Channel-based 33%
• Architectural Synthesis 33%
• Spatial Domain 33%
• Register Allocation 33%
• Synthesis Flow 33%
• Global Interconnect 33%
• Interconnect Resources 33%
• Oriented Path 33%
• Innovations Algorithm 33%
• Temporal Considerations 33%

Computer Science

• Architecture Register 100%
• Communication Architecture 100%
• Experimental Result 50%
• Systems Performance 50%
• Architectural Synthesis 50%
• Register Allocation 50%
• Interconnect Resource 50%