Simulation and investigation of random grain-boundary-induced variabilities for stackable NAND flash using 3-D voronoi grain patterns

This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (H _ch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation.