TY - GEN
T1 - Simulation and Investigation of Gate-Stack Variations in Ferroelectric-FET (FeFET) with Double-Gate Structure
AU - Chang, Lung En
AU - Su, Pin
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This work investigates the impacts of gate-stack variations on double-gate (DG) FeFET NVMs with the aid of TCAD atomistic simulations. The gate-stack variations considered include the interfacial-layer surface roughness and the random ferroelectric-dielectric phase distribution. Our study indicates that both the variability in memory window (MW) and the worst-case MW can be significantly improved by using the DG FeFET (i.e. ferroelectric FinFET) as compared with the ultra-thin-body FeFET counterparts.
AB - This work investigates the impacts of gate-stack variations on double-gate (DG) FeFET NVMs with the aid of TCAD atomistic simulations. The gate-stack variations considered include the interfacial-layer surface roughness and the random ferroelectric-dielectric phase distribution. Our study indicates that both the variability in memory window (MW) and the worst-case MW can be significantly improved by using the DG FeFET (i.e. ferroelectric FinFET) as compared with the ultra-thin-body FeFET counterparts.
UR - http://www.scopus.com/inward/record.url?scp=85163013463&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134347
DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134347
M3 - Conference contribution
AN - SCOPUS:85163013463
T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Y2 - 17 April 2023 through 20 April 2023
ER -