Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation

Feng Chi Wu; Wei Xiang You; Pin Su

doi:10.1109/VLSI-TSA48913.2020.9203737

Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation

Feng Chi Wu
, Wei Xiang You
, Pin Su^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.

Original language	English
Title of host publication	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	78-79
Number of pages	2
ISBN (Electronic)	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203737
State	Published - Aug 2020
Event	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan Duration: 10 Aug 2020 → 13 Aug 2020

Publication series

Name	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Country/Territory	Taiwan
City	Hsinchu
Period	10/08/20 → 13/08/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/VLSI-TSA48913.2020.9203737

Cite this

Wu, F. C., You, W. X., & Su, P. (2020). Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (pp. 78-79). Article 9203737 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203737

Wu, Feng Chi ; You, Wei Xiang ; Su, Pin. / Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation. 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 78-79 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

@inproceedings{3a5454b3e6af4568ae30bfd31d877283,

title = "Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation",

abstract = "In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.",

author = "Wu, \{Feng Chi\} and You, \{Wei Xiang\} and Pin Su",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203737",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "78--79",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "美國",

}

Wu, FC, You, WX & Su, P 2020, Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation. in 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203737, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., pp. 78-79, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203737

Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation. / Wu, Feng Chi; You, Wei Xiang; Su, Pin.
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 78-79 9203737 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wu, Feng Chi

AU - You, Wei Xiang

AU - Su, Pin

PY - 2020/8

Y1 - 2020/8

N2 - In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.

AB - In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.

UR - https://www.scopus.com/pages/publications/85093653037

U2 - 10.1109/VLSI-TSA48913.2020.9203737

DO - 10.1109/VLSI-TSA48913.2020.9203737

M3 - Conference contribution

AN - SCOPUS:85093653037

T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

SP - 78

EP - 79

BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Y2 - 10 August 2020 through 13 August 2020

ER -

Wu FC, You WX, Su P. Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 78-79. 9203737. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203737

Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation

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