Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation

Feng Chi Wu, Wei Xiang You, Pin Su*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.

Original languageEnglish
Title of host publication2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages78-79
Number of pages2
ISBN (Electronic)9781728142326
DOIs
StatePublished - Aug 2020
Event2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan
Duration: 10 Aug 202013 Aug 2020

Publication series

Name2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Country/TerritoryTaiwan
CityHsinchu
Period10/08/2013/08/20

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