TY - GEN
T1 - Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation
AU - Wu, Feng Chi
AU - You, Wei Xiang
AU - Su, Pin
N1 - Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/8
Y1 - 2020/8
N2 - In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.
AB - In this work, we explore device design for ultra-thinbody FeFET NVMs using a new simulation framework by combining TCAD and the ferroelectric minor loop calculation. Our study indicates that, with the fringing capacitance from the spacers, the FeFET exhibits a larger memory window (MW) than that of intrinsic FeFET. For a given MW, the FeFET with high-K spacers allows smaller writing pulse, which is beneficial to endurance and energy efficiency. The FeFET with high-K spacers also exhibits a lower depolarization field, which is crucial to retention.
UR - http://www.scopus.com/inward/record.url?scp=85093653037&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA48913.2020.9203737
DO - 10.1109/VLSI-TSA48913.2020.9203737
M3 - Conference contribution
AN - SCOPUS:85093653037
T3 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
SP - 78
EP - 79
BT - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Y2 - 10 August 2020 through 13 August 2020
ER -
