Simulatable timing model for MOS logic circuit

Shyh-Jye Jou, Wen Zen Shen, Chein Wei Jen, Chung Len Lee

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


A simulatable logic circuit timing model is presented. This timing model is derived from the timing behaviour of MOS devices during transients. Analyses of the errors produced by the use of Newton-Raphson methods to linearise MOS devices and numerical integration algorithms to discretise derivative operators are carried out. Based on these analyses and simulation results the best algorithms are chosen to construct the simulatable timing model. This simulatable timing model consists only of conductances and independent current sources, so is easily incorporated with a lookup table model. A local variable time step control scheme based on the characteristics of the parameters and a simple equation, is implemented, to enhance the simulation speed. A simulator is implemented and the simulated results show that its simulation speed is over 200 times faster than SPICE2G.5 with comparable accuracy.

Original languageEnglish
Pages (from-to)276-284
Number of pages9
JournalIEE Proceedings G: Electronics Circuits and Systems
Issue number6
StatePublished - 1987


  • Computer simulation
  • Computer-aided design
  • Logic
  • Simulation


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