Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform

P. H. Liao; M. H. Kuo; C. W. Tien; Y. L. Chang; P. Y. Hong; T. George; H. C. Lin; P. W. Li

doi:10.1109/VLSIT.2018.8510695

Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform

P. H. Liao, M. H. Kuo, C. W. Tien, Y. L. Chang, P. Y. Hong, T. George, H. C. Lin, P. W. Li

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO₂/Si_1-xGe_x channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO₂ thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (ϵ_comp = 1-3%) of the Si_1-xGe_x are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L_G of 75nm JL n-FETs feature I_ON/I_OFF > 5×10⁸, I_ON > 500μA/μm at V_DS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO₂/Si_1-xGe_x enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	157-158
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510695
State	Published - 25 Oct 2018
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Conference

Conference	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Keywords

Ge
Junctionless
Monolithic integration
Phototransistor

Access to Document

10.1109/VLSIT.2018.8510695

Cite this

Liao, P. H., Kuo, M. H., Tien, C. W., Chang, Y. L., Hong, P. Y., George, T., Lin, H. C., & Li, P. W. (2018). Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 157-158). Article 8510695 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510695

Liao, P. H. ; Kuo, M. H. ; Tien, C. W. et al. / Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 157-158 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{1597ad62b8b947dd88783604925a196c,

title = "Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform",

abstract = "We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO2 thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (ϵcomp = 1-3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. LG of 75nm JL n-FETs feature ION/IOFF > 5×108, ION > 500μA/μm at VDS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.",

keywords = "Ge, Junctionless, Monolithic integration, Phototransistor",

author = "Liao, {P. H.} and Kuo, {M. H.} and Tien, {C. W.} and Chang, {Y. L.} and Hong, {P. Y.} and T. George and Lin, {H. C.} and Li, {P. W.}",

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doi = "10.1109/VLSIT.2018.8510695",

language = "English",

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booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",

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note = "38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

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Liao, PH, Kuo, MH, Tien, CW, Chang, YL, Hong, PY, George, T, Lin, HC & Li, PW 2018, Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510695, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 157-158, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510695

Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform. / Liao, P. H.; Kuo, M. H.; Tien, C. W. et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 157-158 8510695 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kuo, M. H.

AU - Tien, C. W.

AU - Chang, Y. L.

AU - Hong, P. Y.

AU - George, T.

AU - Lin, H. C.

AU - Li, P. W.

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N2 - We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO2 thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (ϵcomp = 1-3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. LG of 75nm JL n-FETs feature ION/IOFF > 5×108, ION > 500μA/μm at VDS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.

AB - We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO2 thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (ϵcomp = 1-3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. LG of 75nm JL n-FETs feature ION/IOFF > 5×108, ION > 500μA/μm at VDS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.

KW - Ge

KW - Junctionless

KW - Monolithic integration

KW - Phototransistor

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Liao PH, Kuo MH, Tien CW, Chang YL, Hong PY, George T et al. Self-organized gate stack of Ge nanosphere/SiO₂/Si_1-xGe_x enables Ge-based monolithically-integrated electronics and photonics on Si platform. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 157-158. 8510695. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510695