SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism

Gary K.C. Huang, Dave Y.W. Lin, John Z.L. Tang, Charles H.P. Wen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


In modern VLSI design flow, timing analysis is crucial for verifying whether a circuit design can operate without errors. Soft-delay effect (SDE), which is a kind of degraded soft error, will make system failed though the circuit has passed the typical timing analysis. Therefore, we propose a soft-delay-aware timing analysis which takes SDE into consideration. Additionally, a path-fixing mechanism is also proposed to fix up the violated paths automatically. Experimental results show that only 1.05% area budget is required averagely that all violated paths can be fixed up. In summary, SDPTA and the path-fixing mechanism are capable of reducing SDE to general circuits without other manual effort.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 29th Asian Test Symposium, ATS 2020
PublisherIEEE Computer Society
ISBN (Electronic)9781728174679
StatePublished - 23 Nov 2020
Event29th IEEE Asian Test Symposium, ATS 2020 - Penang, Malaysia
Duration: 22 Nov 202025 Nov 2020

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference29th IEEE Asian Test Symposium, ATS 2020


  • gate sizing
  • soft delay
  • soft error
  • timing analysis


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