Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

Shiyang Zhu; H. Y. Yu; S. J. Whang; J. H. Chen; Chen Shen; Chunxiang Zhu; S. J. Lee; M. F. Li; D. S.H. Chan; W. J. Yoo; Anyan Du; C. H. Tung; Jagar Singh; Albert Chin; D. L. Kwong

doi:10.1109/LED.2004.826569

Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

Shiyang Zhu^*, H. Y. Yu, S. J. Whang, J. H. Chen, Chen Shen, Chunxiang Zhu, S. J. Lee, M. F. Li, D. S.H. Chan, W. J. Yoo, Anyan Du, C. H. Tung, Jagar Singh, Albert Chin, D. L. Kwong

^*Corresponding author for this work

Research output: Contribution to journal › Letter › peer-review

110 Scopus citations

Abstract

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of I_on/I_off ∼ 10⁷ - 10⁸ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi_2-x S/D, I_on/I_off can reach ∼ 10⁵ at V_ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.

Original language	English
Pages (from-to)	268-270
Number of pages	3
Journal	Ieee Electron Device Letters
Volume	25
Issue number	5
DOIs	https://doi.org/10.1109/LED.2004.826569
State	Published - May 2004

Keywords

High-κ
MOSFET
Metal gate
Schottky

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title = "Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode",

abstract = "This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff ∼ 107 - 108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, Ion/Ioff can reach ∼ 105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.",

keywords = "High-κ, MOSFET, Metal gate, Schottky",

author = "Shiyang Zhu and Yu, {H. Y.} and Whang, {S. J.} and Chen, {J. H.} and Chen Shen and Chunxiang Zhu and Lee, {S. J.} and Li, {M. F.} and Chan, {D. S.H.} and Yoo, {W. J.} and Anyan Du and Tung, {C. H.} and Jagar Singh and Albert Chin and Kwong, {D. L.}",

year = "2004",

month = may,

doi = "10.1109/LED.2004.826569",

language = "English",

volume = "25",

pages = "268--270",

journal = "Ieee Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

AU - Zhu, Shiyang

AU - Yu, H. Y.

AU - Whang, S. J.

AU - Chen, J. H.

AU - Shen, Chen

AU - Zhu, Chunxiang

AU - Lee, S. J.

AU - Li, M. F.

AU - Chan, D. S.H.

AU - Yoo, W. J.

AU - Du, Anyan

AU - Tung, C. H.

AU - Singh, Jagar

AU - Chin, Albert

AU - Kwong, D. L.

PY - 2004/5

Y1 - 2004/5

N2 - This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff ∼ 107 - 108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, Ion/Ioff can reach ∼ 105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.

AB - This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-κ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff ∼ 107 - 108 and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, Ion/Ioff can reach ∼ 105 at Vds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-κ dielectric and metal-gate materials to be used in the future generation CMOS technology.

KW - High-κ

KW - MOSFET

KW - Metal gate

KW - Schottky

UR - http://www.scopus.com/inward/record.url?scp=2442623512&partnerID=8YFLogxK

U2 - 10.1109/LED.2004.826569

DO - 10.1109/LED.2004.826569

M3 - Letter

AN - SCOPUS:2442623512

SN - 0741-3106

VL - 25

SP - 268

EP - 270

JO - Ieee Electron Device Letters

JF - Ieee Electron Device Letters

IS - 5

ER -

Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

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Keywords

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