Scaled contact length with low contact resistance in monolayer 2D channel transistors

Wen Chia Wu, Terry Y.T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen Feng Hsu, Sheng Kai Su, Ang Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying Mei Yang, Kuang I. Lin, Yun Yang Shen, Wen Hao Chang, San Lin Liew, Vincent Hou, Jin Cai, Chung Cheng WuJeff Wu, H. S. Philip Wong, Xinran Wang*, Chao Hsin Chien*, Chao Ching Cheng, Iuliana P. Radu*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS2.

Original languageEnglish
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
StatePublished - 2023
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: 11 Jun 202316 Jun 2023

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period11/06/2316/06/23

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