Scalable mutli-layer barrier synchronization on NoC

Yu Lun Tseng; Kun Hua Huang; Bo-Cheng Lai

doi:10.1109/VLSI-DAT.2016.7482560

Scalable mutli-layer barrier synchronization on NoC

Yu Lun Tseng, Kun Hua Huang, Bo-Cheng Lai

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32×32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482560
State	Published - 31 May 2016
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

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10.1109/VLSI-DAT.2016.7482560

Cite this

Tseng, Y. L., Huang, K. H., & Lai, B-C. (2016). Scalable mutli-layer barrier synchronization on NoC. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482560] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482560

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title = "Scalable mutli-layer barrier synchronization on NoC",

abstract = "Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32×32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.",

author = "Tseng, {Yu Lun} and Huang, {Kun Hua} and Bo-Cheng Lai",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "null ; Conference date: 25-04-2016 Through 27-04-2016",

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Tseng, YL, Huang, KH & Lai, B-C 2016, Scalable mutli-layer barrier synchronization on NoC. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482560, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-DAT.2016.7482560

Scalable mutli-layer barrier synchronization on NoC. / Tseng, Yu Lun; Huang, Kun Hua; Lai, Bo-Cheng.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482560 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32×32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.

AB - Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32×32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.

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Scalable mutli-layer barrier synchronization on NoC

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