TY - GEN
T1 - Scalable automaton matching for high-speed deep content inspection
AU - Lin, Ying-Dar
AU - Tseng, Kuo Kun
AU - Hung, Chen Chou
AU - Lai, Yuan Cheng
PY - 2007/10/18
Y1 - 2007/10/18
N2 - String matching plays a central role in content inspection applications such as intrusion detection, anti-virus, anti-spam and Web filtering. Because they are computation and memory intensive, software matching algorithms are insufficient in meeting the high-speed performance. Thus, offloading packet content inspection to dedicated hardware seems inevitable. This paper presents a scalable automaton matching (SAM) design, which uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing. The root-indexing can match multiple bytes in one single matching, and the pre-hashing can be used to avoid bitmap AC matching, which is a cycle-consuming operation. In the implementation of the Xilinx Vertex4P FPGA platform, the proposed hardware architecture can achieve almost 10.7 Gbps and support the largest pattern set, which is 7.65 times faster than the original bitmap AC in the average case. Further, SAM is feasible for either internal or external memory architecture. The internal memory architecture provides high performance, and the external memory architecture provides high scalability of patterns.
AB - String matching plays a central role in content inspection applications such as intrusion detection, anti-virus, anti-spam and Web filtering. Because they are computation and memory intensive, software matching algorithms are insufficient in meeting the high-speed performance. Thus, offloading packet content inspection to dedicated hardware seems inevitable. This paper presents a scalable automaton matching (SAM) design, which uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing. The root-indexing can match multiple bytes in one single matching, and the pre-hashing can be used to avoid bitmap AC matching, which is a cycle-consuming operation. In the implementation of the Xilinx Vertex4P FPGA platform, the proposed hardware architecture can achieve almost 10.7 Gbps and support the largest pattern set, which is 7.65 times faster than the original bitmap AC in the average case. Further, SAM is feasible for either internal or external memory architecture. The internal memory architecture provides high performance, and the external memory architecture provides high scalability of patterns.
KW - Content filtering
KW - Coprocessor
KW - Finite automata
KW - Hashing
KW - String matching
UR - http://www.scopus.com/inward/record.url?scp=35248838956&partnerID=8YFLogxK
U2 - 10.1109/AINAW.2007.318
DO - 10.1109/AINAW.2007.318
M3 - Conference contribution
AN - SCOPUS:35248838956
SN - 0769528473
SN - 9780769528472
T3 - Proceedings - 21st International Conference on Advanced Information Networking and Applications Workshops/Symposia, AINAW'07
SP - 858
EP - 863
BT - Proceedings - 21st International Conference on Advanced Information Networking and ApplicationsWorkshops/Symposia, AINAW'07
T2 - 21st International Conference on Advanced Information Networking and ApplicationsWorkshops/Symposia, AINAW'07
Y2 - 21 May 2007 through 23 May 2007
ER -