Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design

C. H. Wu*, J. Liu, X. T. Zheng, Y. M. Tseng, M. Kobayashi, V. P.H. Hu*, C. J. Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This work systematically demonstrates a novel recovery scheme for MFIS-FeFET memory arrays involving device fabrication and circuit integration. For the first time, the timing to initiate recovery to prolong the endurance of FeFETs is studied. A 100-ns fast-unipolar pulsing (FUP) recovery treatment at optimized timing is demonstrated with significantly extending endurance cycles by a factor of 102, together with a nearly zero loss (0.02 %) in memory window (MW) per recovery period and a low MW fluctuation. An ultra-low recovery-induced time loss ratio of 5×10-5 % is achieved. Based on the developed scheme, we propose a self-tracking recovery circuit design utilizing current-mode memory sensing to monitor the degree of fatigue and automatically trigger the recovery operation.

Original languageEnglish
Title of host publication2023 International Electron Devices Meeting, IEDM 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350327670
DOIs
StatePublished - 2023
Event2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States
Duration: 9 Dec 202313 Dec 2023

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2023 International Electron Devices Meeting, IEDM 2023
Country/TerritoryUnited States
CitySan Francisco
Period9/12/2313/12/23

Fingerprint

Dive into the research topics of 'Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design'. Together they form a unique fingerprint.

Cite this