Resistor-less design of power-rail ESD clamp circuit in nanoscale CMOS technology

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    13 Scopus citations


    A resistor-less power-rail electrostatic discharge (ESD) clamp circuit realized with only thin-gate-oxide devices and with a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By skillfully utilizing the gate leakage current to realize the equivalent resistor in the ESD-transient detection circuit, the RC-based ESD detection mechanism can be achieved without using an actual resistor to significantly reduce the layout area in I/O cells. From the measured results, the new proposed power-rail ESD clamp circuit with an SCR width of 45 μm can achieve 5-kV human-body-model and 400-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current of 1.43 nA at room temperature under the normal circuit operating condition with 1-V bias.

    Original languageEnglish
    Article number6335469
    Pages (from-to)3456-3463
    Number of pages8
    JournalIEEE Transactions on Electron Devices
    Issue number12
    StatePublished - 2012


    • Electrostatic discharge (ESD)
    • gate leakage
    • power-rail ESD clamp circuit
    • silicon-controlled rectifier (SCR)


    Dive into the research topics of 'Resistor-less design of power-rail ESD clamp circuit in nanoscale CMOS technology'. Together they form a unique fingerprint.

    Cite this