REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory

Bo Cheng Lai*, Bo Ya Chen, Bo En Chen, Yi Da Hsin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Supporting multiple write ports is one of the main challenges when designing algorithmic multiported memory (AMM). AMM supports concurrent accesses by cooperating multiple, low-complexity memory modules together with logical operations. When scaling the number of write ports, the nontable-based approaches quadratically increase the number of memory modules, whereas the table-based approaches tend to introduce complex lookup tables and access handling logics. In this article, we introduce REMAP+, an efficient banking architecture to support multiple writes. We optimize the pipeline of REMAP+ to achieve high access bandwidth and more efficient table access. We also exploit the structured architecture of REMAP+ and propose a systematic design flow to automate the scaling of write ports and optimization of banking. Comprehensive analysis is presented to reveal the insight into design features and concerns. Based on extensive experiments, we have shown that REMAP+ outperforms the existing write schemes (XOR, live value table (LVT), and REMAP) with higher bandwidth (49%, 50%, 18%), lower energy (28%, 49%, 54%), and smaller area (43%, 37%, 35%).

Original languageEnglish
Article number8939326
Pages (from-to)660-671
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 2020


  • Algorithmic multiported memory (AMM)
  • banking structure
  • memory architecture
  • multiple writes


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