@inproceedings{73387568fe0342108e26cebc71b2d812,
title = "Reliability-aware design automation flow for analog circuits",
abstract = "Manually designing analog circuits is often considered as a difficult task that takes a lot of time. If a design automation environment is available for analog circuits, it is useful for designers to cope with the increasing challenges in advance process. In this paper, a reliability-aware circuit sizing technique is proposed to consider process variation, circuit aging, and layout-dependent effects simultaneously. A reliability-aware analog layout automation technique is also proposed to consider both placement and routing while improving the reliability of the generated layout. These reliability-aware design automation techniques have been integrated to build a complete synthesis environment from specifications to layout. As shown in the experimental results, the proposed automation flow does help designers solve the reliability issues efficiently.",
keywords = "analog design automation, circuit reliability",
author = "Chien-Nan Liu and Chen, {Yen Lung} and Liu, {Tsung Yu} and Chen, {Tai Chen}",
year = "2016",
month = feb,
day = "8",
doi = "10.1109/ISOCC.2015.7401682",
language = "English",
series = "ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--2",
booktitle = "ISOCC 2015 - International SoC Design Conference",
address = "美國",
note = "12th International SoC Design Conference, ISOCC 2015 ; Conference date: 02-11-2015 Through 05-11-2015",
}