Reliability assessment of high-power GaN-HEMT devices with different buffers under influence of gate bias and high-temperature tests

Shivendra K. Rathaur*, Le Trung Hieu, Abhisek Dixit, Edward Yi Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This study compares Vth-instability in D-mode MIS-HEMT devices between two epitaxial layers, AlN/AlGaN/GaN superlattice-W1, and three-step graded AlGaN-W2. Experimental results demonstrate that W1 exhibits ∼13% less Vth-instability compared to W2, with distinct degradation regions at specific voltage ranges. With temperature variation (30 °C-150 °C), these regions are justified and revealed small positive Vth-shifts due to electron trapping, leading to temporary degradation, followed-by negative Vth-shifts from positive charge injection, culminating in catastrophic degradation attributing impact ionization at 30 °C during 0-30 V gate-step stress, with permanent failure observed. Analysis indicates W1-devices are more efficient and stable. Also, both layers operate reliably till VGS = 18 V, with ∼3% minor Vth instability.

Original languageEnglish
Article number076501
JournalApplied Physics Express
Volume17
Issue number7
DOIs
StatePublished - 1 Jul 2024

Keywords

  • GaN-HEMT
  • semiconductor device process
  • semiconductor device reliability
  • semiconductor device testing

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