TY - GEN
T1 - Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids
AU - Lin, Mark Po Hung
AU - Lee, Chou Chen
AU - Hsieh, Yi Chao
N1 - Publisher Copyright:
© 2024 ACM.
PY - 2024/3/12
Y1 - 2024/3/12
N2 - Analog placement is a crucial phase in analog integrated circuit synthesis, impacting the quality and performance of the final circuits. This process involves determining the physical positions of analog building blocks while minimizing chip area and interconnecting wire-length. Existing methodologies often rely on the simulated-annealing (SA) approach, prioritizing constraints like symmetry-island, proximity, and well-island. We present a novel reinforcement learning (RL) based analog placement methodology on the bounded-sliceline grid (BSG) structure. Introducing a hierarchical clustering feature in BSG, we address well-island, proximity, and symmetry constraints. In experimental comparisons with the SA approach, our RL-based method exhibits superior placement quality across various analog circuits.
AB - Analog placement is a crucial phase in analog integrated circuit synthesis, impacting the quality and performance of the final circuits. This process involves determining the physical positions of analog building blocks while minimizing chip area and interconnecting wire-length. Existing methodologies often rely on the simulated-annealing (SA) approach, prioritizing constraints like symmetry-island, proximity, and well-island. We present a novel reinforcement learning (RL) based analog placement methodology on the bounded-sliceline grid (BSG) structure. Introducing a hierarchical clustering feature in BSG, we address well-island, proximity, and symmetry constraints. In experimental comparisons with the SA approach, our RL-based method exhibits superior placement quality across various analog circuits.
KW - analog placement
KW - bounded-sliceline grid
KW - machine learning
KW - proximity
KW - reinforcement learning
KW - simulated annealing
KW - symmetry
UR - http://www.scopus.com/inward/record.url?scp=85188442660&partnerID=8YFLogxK
U2 - 10.1145/3626184.3635281
DO - 10.1145/3626184.3635281
M3 - Conference contribution
AN - SCOPUS:85188442660
T3 - Proceedings of the International Symposium on Physical Design
SP - 143
EP - 150
BT - ISPD 2024 - Proceedings of the 2024 International Symposium on Physical Design
PB - Association for Computing Machinery
T2 - 33rd International Symposium on Physical Design, ISPD 2024
Y2 - 12 March 2024 through 15 March 2024
ER -