Reduced processing element architecture for parallel local image processing

Po-Ning Chen; Yung Sheng Chen; Wen Using Hsu

doi:10.1080/02533839.1987.9677029

Reduced processing element architecture for parallel local image processing

Po-Ning Chen, Yung Sheng Chen, Wen Using Hsu^*

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real-time performance. For large-sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3X3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real-time performance.

Original language	English
Pages (from-to)	701-707
Number of pages	7
Journal	Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an
Volume	10
Issue number	6
DOIs	https://doi.org/10.1080/02533839.1987.9677029
State	Published - 1 Jan 1987

Keywords

Convolution
Image processing
Local operation

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10.1080/02533839.1987.9677029

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title = "Reduced processing element architecture for parallel local image processing",

abstract = "The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real-time performance. For large-sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3X3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real-time performance.",

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author = "Po-Ning Chen and Chen, {Yung Sheng} and Hsu, {Wen Using}",

year = "1987",

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Reduced processing element architecture for parallel local image processing. / Chen, Po-Ning; Chen, Yung Sheng; Hsu, Wen Using.
In: Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, Vol. 10, No. 6, 01.01.1987, p. 701-707.

Research output: Contribution to journal › Article › peer-review

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AB - The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real-time performance. For large-sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3X3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real-time performance.

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Reduced processing element architecture for parallel local image processing

Abstract

Keywords

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