Reconfigurable low power MPEG-4 texture decoder IP design

Chien Chang Lin; Hsiu Cheng Chang; Kuan Hung Chen; Jiun-In  Guo

doi:10.1109/APCCAS.2004.1412715

Reconfigurable low power MPEG-4 texture decoder IP design

Chien Chang Lin^*, Hsiu Cheng Chang, Kuan Hung Chen, Jiun-In Guo

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

In this paper, we propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35μm CMOS technology.

Original language	English
Pages	153-156
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1412715
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

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10.1109/APCCAS.2004.1412715

Cite this

@conference{61f7a2a617924d878a7e14adc8dc3918,

title = "Reconfigurable low power MPEG-4 texture decoder IP design",

abstract = "In this paper, we propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35μm CMOS technology.",

author = "Lin, {Chien Chang} and Chang, {Hsiu Cheng} and Chen, {Kuan Hung} and Jiun-In Guo",

year = "2004",

month = dec,

doi = "10.1109/APCCAS.2004.1412715",

language = "English",

pages = "153--156",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

TY - CONF

T1 - Reconfigurable low power MPEG-4 texture decoder IP design

AU - Lin, Chien Chang

AU - Chang, Hsiu Cheng

AU - Chen, Kuan Hung

AU - Guo, Jiun-In

PY - 2004/12

Y1 - 2004/12

N2 - In this paper, we propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35μm CMOS technology.

AB - In this paper, we propose a reconfigurable low-power MPEG-4 texture decoder IP design to support up to MPEG-4 SP@L3 video decoding. The proposed texture decoder IP includes an optimized DC/AC prediction and low-power adder-based inverse discrete cosine transform (IDCT) processor. In order to increase the flexibility, the proposed design can be reconfigured to decode MPEG-4 video with different frame sizes without modifying the architecture. For reducing the power consumption, we have re-arranged the MPEG-4 texture decoding flow, exploited efficient adder-based algorithm and DPGC-based architecture for IDCT processor, and adopted the zero vector detection technique in skipping the IDCT operations on zero data. The implementation results show that the proposed texture decoder IP design costs 11698 gates and 9472 bits memory for supporting the MPEG-4 CIF video texture decoding @ 30Hz under the TSMC 0.35μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=21644482982&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2004.1412715

DO - 10.1109/APCCAS.2004.1412715

M3 - Paper

AN - SCOPUS:21644482982

SP - 153

EP - 156

T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

Reconfigurable low power MPEG-4 texture decoder IP design

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