Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS

Wen Shen Wuen; Shen Fong Liu; Kuang Yu Chen; Kuei-Ann Wen

doi:10.1109/APMC.1999.829905

Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS

Wen Shen Wuen^*, Shen Fong Liu, Kuang Yu Chen, Kuei-Ann Wen

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with f_T of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB.

Original language	English
Pages	460-463
Number of pages	4
DOIs	https://doi.org/10.1109/APMC.1999.829905
State	Published - 1 Dec 1999
Event	1999 Asia Pacific Microwave Conference (APMC'99) 'Microwaves Enter the 21st Century' - Singapore, Singapore Duration: 30 Nov 1999 → 3 Dec 1999

Conference

Conference	1999 Asia Pacific Microwave Conference (APMC'99) 'Microwaves Enter the 21st Century'
City	Singapore, Singapore
Period	30/11/99 → 3/12/99

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10.1109/APMC.1999.829905

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title = "Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS",

abstract = "The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with fT of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB.",

author = "Wuen, {Wen Shen} and Liu, {Shen Fong} and Chen, {Kuang Yu} and Kuei-Ann Wen",

year = "1999",

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AU - Wuen, Wen Shen

AU - Liu, Shen Fong

AU - Chen, Kuang Yu

AU - Wen, Kuei-Ann

PY - 1999/12/1

Y1 - 1999/12/1

N2 - The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with fT of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB.

AB - The paper presents the design and implementation of receiver front-end chipsets for 2.4-GHz 802.11 Wireless LAN. The chipsets consist of low noise amplifier and down conversion mixers in single-balanced and double-balanced structures. The LNA is designed with optimum bias technique for minimizing noise figure. The front-end chipsets are fabricated with 0.5-μm BiCMOS process with fT of 13-GHz and packaged in SOP8 package. It is presented that under 802.11 standard specified system link budget, the chipset hit the design performance and leave the design margin of 4.89 dB.

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Y2 - 30 November 1999 through 3 December 1999

ER -

Receiver front-end chipsets for 2.4-GHz Wireless LAN in 0.5 μm BiCMOS

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