Realization of a systematic bit-wise decomposition metric

Chia Wei Chang; Po-Ning Chen; Yunghsiang S. Han

doi:10.1109/APCCAS.2004.1413067

Realization of a systematic bit-wise decomposition metric

Chia Wei Chang^*, Po-Ning Chen, Yunghsiang S. Han

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

Original language	English
Pages	1065-1068
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1413067
State	Published - 6 Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

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10.1109/APCCAS.2004.1413067

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abstract = "In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.",

author = "Chang, {Chia Wei} and Po-Ning Chen and Han, {Yunghsiang S.}",

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AB - In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.

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Realization of a systematic bit-wise decomposition metric

Abstract

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