Abstract
Methods are presented to reduce both the onboard storage volume and transmission-rate requirement for NASA's two high-rate instruments the HIRIS high-resolution imaging spectrometer and the synthetic-Aperture radar (SAR) to be flown as research facility instruments on the NASA earth observing system (EOS) polar-orbiting platforms. A distortion-free coding scheme capable of providing a factor of three-to-one in data compression is described. The data compression scheme is a variant of the block adaptive rate controlled (BARC) method. Special emphasis is placed on the changes made to accommodate the VLSI design approach. A conceptual design utilizing the VLSI parallel/pipelined architecture capable of meeting real-time processing requirement is provided. The architecture consists of a parallel array of VLSI compressor modules with each module built on a single customized VLSI chip. It is capable of achieving throughput rate at one gigabit per second.
Original language | English |
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Pages (from-to) | 155-160 |
Number of pages | 6 |
Journal | EASCON Record: IEEE Electronics and Aerospace Systems Convention |
State | Published - 1 Dec 1987 |
Event | EASCON Rec 20th, Annu Electron and Aerosp Syst Conf - Technol for Space Leadership Conf Proc - Washington, DC, USA Duration: 14 Oct 1987 → 16 Oct 1987 |