Real-time computing of optical flow using adaptive VLSI neuroprocessors

Wai-Chi  Fang; Bing J. Sheu; Ji Chien Lee

doi:10.1109/ICCD.1990.130180

Real-time computing of optical flow using adaptive VLSI neuroprocessors

Wai-Chi Fang^*, Bing J. Sheu, Ji Chien Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.

Original language	English
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	122-125
Number of pages	4
ISBN (Print)	O81862079X
DOIs	https://doi.org/10.1109/ICCD.1990.130180
State	Published - 1 Sep 1990
Event	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: 17 Sep 1990 → 19 Sep 1990

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Conference

Conference	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
City	Cambridge, MA, USA
Period	17/09/90 → 19/09/90

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10.1109/ICCD.1990.130180

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Fang, W-C., Sheu, B. J., & Lee, J. C. (1990). Real-time computing of optical flow using adaptive VLSI neuroprocessors. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 122-125). (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). Publ by IEEE. https://doi.org/10.1109/ICCD.1990.130180

@inproceedings{060e225d16734b808ae1a727c723747c,

title = "Real-time computing of optical flow using adaptive VLSI neuroprocessors",

abstract = "The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.",

author = "Wai-Chi Fang and Sheu, {Bing J.} and Lee, {Ji Chien}",

year = "1990",

month = sep,

day = "1",

doi = "10.1109/ICCD.1990.130180",

language = "English",

isbn = "O81862079X",

series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

publisher = "Publ by IEEE",

pages = "122--125",

booktitle = "Proceedings - IEEE International Conference on Computer Design",

note = "Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",

}

Fang, W-C, Sheu, BJ & Lee, JC 1990, Real-time computing of optical flow using adaptive VLSI neuroprocessors. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, Publ by IEEE, pp. 122-125, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 17/09/90. https://doi.org/10.1109/ICCD.1990.130180

Real-time computing of optical flow using adaptive VLSI neuroprocessors. / Fang, Wai-Chi ; Sheu, Bing J.; Lee, Ji Chien.
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 122-125 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Real-time computing of optical flow using adaptive VLSI neuroprocessors

AU - Fang, Wai-Chi

AU - Sheu, Bing J.

AU - Lee, Ji Chien

PY - 1990/9/1

Y1 - 1990/9/1

N2 - The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.

AB - The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips.

UR - http://www.scopus.com/inward/record.url?scp=0025486979&partnerID=8YFLogxK

U2 - 10.1109/ICCD.1990.130180

DO - 10.1109/ICCD.1990.130180

M3 - Conference contribution

AN - SCOPUS:0025486979

SN - O81862079X

T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

SP - 122

EP - 125

BT - Proceedings - IEEE International Conference on Computer Design

PB - Publ by IEEE

T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90

Y2 - 17 September 1990 through 19 September 1990

ER -

Real-time computing of optical flow using adaptive VLSI neuroprocessors

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