Rapid C to FPGA prototyping with multithreaded emulation engine

Shin Kai Chen; Bing Shiun Wang; Tay Jyi Lin; Chih-Wei Liu

doi:10.1109/ISCAS.2007.378476

Rapid C to FPGA prototyping with multithreaded emulation engine

Shin Kai Chen^*, Bing Shiun Wang, Tay Jyi Lin, Chih-Wei Liu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

Abstract

FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GHz Pentium D PC.

Original language	English
Article number	4252658
Pages (from-to)	409-412
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2007.378476
State	Published - 27 Sep 2007
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 May 2007 → 30 May 2007

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title = "Rapid C to FPGA prototyping with multithreaded emulation engine",

abstract = "FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GHz Pentium D PC.",

author = "Chen, {Shin Kai} and Wang, {Bing Shiun} and Lin, {Tay Jyi} and Chih-Wei Liu",

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pages = "409--412",

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note = "2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

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AU - Chen, Shin Kai

AU - Wang, Bing Shiun

AU - Lin, Tay Jyi

AU - Liu, Chih-Wei

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N2 - FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GHz Pentium D PC.

AB - FPGA prototyping is preferred over software simulations for its more convincing & realistic behaviours and fast simulation time. However, it is usually possible after the RTL design is done, which prevents extensive design space exploration. This paper describes an early-stage FPGA prototyping flow, which starts from C sources, through hardware/software partitioning with transaction-level modelling (TLM), to the RTL design. We also propose a FPGA-customized multithreaded emulation engine for TLM prototyping. Compared with the OpenRISC core, the proposed engine saves 43.08% datapath complexity while improving the operating frequency by 60.67%. Moreover, our FPGA prototype for JPEG at TLM can compress 37.16 color QCIF frames per second, which is 4.5X faster than SystemC simulation on a 3GHz Pentium D PC.

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Y2 - 27 May 2007 through 30 May 2007

ER -

Rapid C to FPGA prototyping with multithreaded emulation engine

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