Random pattern generation for post-silicon validation of DDR3 SDRAM

Hao Yu Yang, Shih Hua Kuo, Tzu Hsuan Huang, Chi Hung Chen, Chris Lin, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
PublisherIEEE Computer Society
ISBN (Electronic)9781479975976
StatePublished - 1 Jun 2015
Event2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
Duration: 27 Apr 201529 Apr 2015

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2015 33rd IEEE VLSI Test Symposium, VTS 2015
Country/TerritoryUnited States


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