Prototype IC with WDDL and differential routing - DPA resistance assessment

Kris Tiri; David Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede

doi:10.1007/11545262_26

Prototype IC with WDDL and differential routing - DPA resistance assessment

Kris Tiri^*, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

130 Scopus citations

Abstract

Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

Original language	English
Pages (from-to)	354-365
Number of pages	12
Journal	Lecture Notes in Computer Science
Volume	3659
DOIs	https://doi.org/10.1007/11545262_26
State	Published - 4 Nov 2005
Event	7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005 - Edinburgh, United Kingdom Duration: 29 Aug 2005 → 1 Sep 2005

Keywords

Countermeasure
Differential power analysis (DPA)
Differential routing
Dual rail with precharge
Parasitic capacitance matching
Side-channel attack (SCA)
Wave dynamic differential logic (WDDL)

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10.1007/11545262_26

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title = "Prototype IC with WDDL and differential routing - DPA resistance assessment",

abstract = "Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.",

keywords = "Countermeasure, Differential power analysis (DPA), Differential routing, Dual rail with precharge, Parasitic capacitance matching, Side-channel attack (SCA), Wave dynamic differential logic (WDDL)",

author = "Kris Tiri and David Hwang and Alireza Hodjat and Bo-Cheng Lai and Shenglin Yang and Patrick Schaumont and Ingrid Verbauwhede",

year = "2005",

month = nov,

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doi = "10.1007/11545262_26",

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T1 - Prototype IC with WDDL and differential routing - DPA resistance assessment

AU - Tiri, Kris

AU - Hwang, David

AU - Hodjat, Alireza

AU - Lai, Bo-Cheng

AU - Yang, Shenglin

AU - Schaumont, Patrick

AU - Verbauwhede, Ingrid

PY - 2005/11/4

Y1 - 2005/11/4

N2 - Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

AB - Wave dynamic differential logic combined with differential routing is a working, practical technique to thwart side-channel power attacks. Measurement-based experimental results show that a differential power analysis attack on a prototype IC, fabricated in 0.18μm CMOS, does not disclose the entire secret key of the AES algorithm at 1,500,000 measurement acquisitions. This makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

KW - Countermeasure

KW - Differential power analysis (DPA)

KW - Differential routing

KW - Dual rail with precharge

KW - Parasitic capacitance matching

KW - Side-channel attack (SCA)

KW - Wave dynamic differential logic (WDDL)

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DO - 10.1007/11545262_26

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AN - SCOPUS:27244438768

SN - 0302-9743

VL - 3659

SP - 354

EP - 365

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

T2 - 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005

Y2 - 29 August 2005 through 1 September 2005

ER -

Prototype IC with WDDL and differential routing - DPA resistance assessment

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Keywords

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