Process technological analysis for dynamic characteristic improvement of 16-nm HKMG bulk FinFET CMOS circuits

Ping Hsun Su, Yi-ming Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this work, we study dynamic characteristic of digital CMOS circuits of 16-nm HKMG bulk FinFET devices by optimizing fabrication windows of inline parameters. Key process parameters are ranked according to integrated circuit quiescent current (IDDQ) and delay of ring oscillators. IDDQ and delay are affected by the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant. Dependencies of operational frequency and IDDQ on the on-state current ratio of N/P FinFET devices are examined. By replacing dual spacers with single ones will improve the uniformity of implantation; consequently, the variation of IDDQ can be reduced from 252 to 37 nA significantly.

Original languageEnglish
Title of host publication16th International Conference on Nanotechnology - IEEE NANO 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages812-815
Number of pages4
ISBN (Electronic)9781509039142
DOIs
StatePublished - 21 Nov 2016
Event16th IEEE International Conference on Nanotechnology - IEEE NANO 2016 - Sendai, Japan
Duration: 22 Aug 201625 Aug 2016

Publication series

Name16th International Conference on Nanotechnology - IEEE NANO 2016

Conference

Conference16th IEEE International Conference on Nanotechnology - IEEE NANO 2016
Country/TerritoryJapan
CitySendai
Period22/08/1625/08/16

Keywords

  • Bulk FinFETs
  • Frequency
  • Inline process parameters
  • Integrated circuit quiescent current
  • Ring oscillators

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