Process integration of composite high-k tunneling dielectric for nanocrystal based carbon nanotube memory

Recently, metal nanocrystal (NC) based carbon nanotube (CNT) memory has been demonstrated with sub-5V low bias programming, single electron sensitivity, but poor room-temperature retention. The process integration of an ultra-thin tunnel dielectric is essential for lateral, vertical scaling and reliable room-temperature operations. Low defect density and conformal deposition on the nanotube are required to enhance the performance as a tunnel barrier. Additionally, Au contamination in the CNT decreases the on/off current ratio in the CNTFETs by substantially increasing the off current. Consequently, the dielectric should function as a good diffusion barrier for Au in the nanocrystals. We have explored composite tunneling dielectric film with SiO ₂ seed layer for conformal high-k deposition to demonstrate minimal Au contamination and improved retention. Room temperature retention of better than three days has been observed.