Process integration of composite high-k tunneling dielectric for nanocrystal based carbon nanotube memory

Udayan Ganguly*, Tuo-Hung Hou, Edwin Chihchuan Kan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Recently, metal nanocrystal (NC) based carbon nanotube (CNT) memory has been demonstrated with sub-5V low bias programming, single electron sensitivity, but poor room-temperature retention. The process integration of an ultra-thin tunnel dielectric is essential for lateral, vertical scaling and reliable room-temperature operations. Low defect density and conformal deposition on the nanotube are required to enhance the performance as a tunnel barrier. Additionally, Au contamination in the CNT decreases the on/off current ratio in the CNTFETs by substantially increasing the off current. Consequently, the dielectric should function as a good diffusion barrier for Au in the nanocrystals. We have explored composite tunneling dielectric film with SiO 2 seed layer for conformal high-k deposition to demonstrate minimal Au contamination and improved retention. Room temperature retention of better than three days has been observed.

Original languageEnglish
Title of host publicationNanostructured and Patterned Materials for Information Storage
PublisherMaterials Research Society
Number of pages6
ISBN (Print)9781604234138
StatePublished - 2006
Event2006 MRS Fall Meeting - Boston, MA, United States
Duration: 27 Nov 20061 Dec 2006

Publication series

NameMaterials Research Society Symposium Proceedings
ISSN (Print)0272-9172


Conference2006 MRS Fall Meeting
Country/TerritoryUnited States
CityBoston, MA


Dive into the research topics of 'Process integration of composite high-k tunneling dielectric for nanocrystal based carbon nanotube memory'. Together they form a unique fingerprint.

Cite this