Process and Structure Considerations for the Post FinFET Era

Chun-Jung Su; Po Jung Sung; Kuo Hsing Kao; Yao Jen Lee; Wen Fa Wu; Wen-Kuan Yeh

doi:10.1109/SNW50361.2020.9131422

Process and Structure Considerations for the Post FinFET Era

Chun-Jung Su^*, Po Jung Sung, Kuo Hsing Kao, Yao Jen Lee, Wen Fa Wu, Wen-Kuan Yeh

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

Original language	English
Title of host publication	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-14
Number of pages	2
ISBN (Electronic)	9781728197357
DOIs	https://doi.org/10.1109/SNW50361.2020.9131422
State	Published - Jun 2020
Event	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States Duration: 13 Jun 2020 → 14 Jun 2020

Publication series

Name	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Country/Territory	United States
City	Honolulu
Period	13/06/20 → 14/06/20

Keywords

CMOS
FinFET
nanosheet
nanowire

Access to Document

10.1109/SNW50361.2020.9131422

Cite this

Su, C.-J., Sung, P. J., Kao, K. H., Lee, Y. J., Wu, W. F., & Yeh, W.-K. (2020). Process and Structure Considerations for the Post FinFET Era. In 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 (pp. 13-14). Article 9131422 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW50361.2020.9131422

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abstract = "Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.",

keywords = "CMOS, FinFET, nanosheet, nanowire",

author = "Chun-Jung Su and Sung, {Po Jung} and Kao, {Kuo Hsing} and Lee, {Yao Jen} and Wu, {Wen Fa} and Wen-Kuan Yeh",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 ; Conference date: 13-06-2020 Through 14-06-2020",

year = "2020",

month = jun,

doi = "10.1109/SNW50361.2020.9131422",

language = "English",

series = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",

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Su, C-J, Sung, PJ, Kao, KH, Lee, YJ, Wu, WF & Yeh, W-K 2020, Process and Structure Considerations for the Post FinFET Era. in 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020., 9131422, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Institute of Electrical and Electronics Engineers Inc., pp. 13-14, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Honolulu, United States, 13/06/20. https://doi.org/10.1109/SNW50361.2020.9131422

Process and Structure Considerations for the Post FinFET Era. / Su, Chun-Jung; Sung, Po Jung; Kao, Kuo Hsing et al.
2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 13-14 9131422 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yeh, Wen-Kuan

PY - 2020/6

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AB - Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

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ER -

Process and Structure Considerations for the Post FinFET Era

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Keywords

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