TY - GEN
T1 - Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator
AU - Kao, Jui I.
AU - Lu, Wei
AU - Huang, Po Tsang
AU - Chen, Hung Ming
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - SRAM-based Computing-in-memory (CIM) circuits have been demonstrated as a promising solution to effectively accelerate the inference of convolutional neural networks (CNNs) by shifting computation into the memory arrays. However, the advantages of CIM accelerators will disappear as increasing the bit precision and adopting advanced process technology due to the overhead caused by ADC/DAC and poor technology scaling capability of analog circuits. In this paper, a hybrid digital-CIM accelerator was proposed to solve above problems and the weights and activations of different layers are quantized to different precision (high, medium, and low precision). Moreover, precision-aware workload distribution and dataflow are proposed for the hybrid digital-CIM accelerator. Overall, the proposed accelerator can achieve 12.481 TOPS/W.
AB - SRAM-based Computing-in-memory (CIM) circuits have been demonstrated as a promising solution to effectively accelerate the inference of convolutional neural networks (CNNs) by shifting computation into the memory arrays. However, the advantages of CIM accelerators will disappear as increasing the bit precision and adopting advanced process technology due to the overhead caused by ADC/DAC and poor technology scaling capability of analog circuits. In this paper, a hybrid digital-CIM accelerator was proposed to solve above problems and the weights and activations of different layers are quantized to different precision (high, medium, and low precision). Moreover, precision-aware workload distribution and dataflow are proposed for the hybrid digital-CIM accelerator. Overall, the proposed accelerator can achieve 12.481 TOPS/W.
KW - hybrid digital-CIM
KW - precision-aware
UR - http://www.scopus.com/inward/record.url?scp=85148473132&partnerID=8YFLogxK
U2 - 10.1109/ISOCC56007.2022.10031486
DO - 10.1109/ISOCC56007.2022.10031486
M3 - Conference contribution
AN - SCOPUS:85148473132
T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022
SP - 171
EP - 172
BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th International System-on-Chip Design Conference, ISOCC 2022
Y2 - 19 October 2022 through 22 October 2022
ER -