TY - GEN
T1 - Pre-RTL DNN Hardware Evaluator with Fused Layer Support
AU - Yang, Chih Chyau
AU - Chang, Tian Sheuan
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution. However, lengthy design process and fast evolving DNN models make hardware evaluation hard to meet the time to market need. This paper proposes a pre-RTL DNN hardware evaluator that supports conventional layer-by-layer processing as well as the fused layer processing for low external bandwidth requirement. The evaluator supports two state-of-The-Art accelerator architectures and finds the best hardware and layer fusion group. The experimental results show the layer fusion scheme can achieve 55.6% memory bandwidth reduction, 36.7% latency improvement and 49.2% energy reduction compared with layer-by-layer operation.
AB - With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution. However, lengthy design process and fast evolving DNN models make hardware evaluation hard to meet the time to market need. This paper proposes a pre-RTL DNN hardware evaluator that supports conventional layer-by-layer processing as well as the fused layer processing for low external bandwidth requirement. The evaluator supports two state-of-The-Art accelerator architectures and finds the best hardware and layer fusion group. The experimental results show the layer fusion scheme can achieve 55.6% memory bandwidth reduction, 36.7% latency improvement and 49.2% energy reduction compared with layer-by-layer operation.
KW - deep learning accelerator
KW - layer fusion
KW - neural network evaluator
UR - http://www.scopus.com/inward/record.url?scp=85123374582&partnerID=8YFLogxK
U2 - 10.1109/ISOCC53507.2021.9614027
DO - 10.1109/ISOCC53507.2021.9614027
M3 - Conference contribution
AN - SCOPUS:85123374582
T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021
SP - 83
EP - 84
BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International System-on-Chip Design Conference, ISOCC 2021
Y2 - 6 October 2021 through 9 October 2021
ER -