Power-aware scheduling for parallel security processors with analytical models

Yung Chia Lin*, Yi-Ping You, Chung Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, Ting Ting Hwang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multiple-domain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper1, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogeneous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources that are of correlations. Experiments are done in the prototypical environments for our security processors and the results show that significant energy reductions can be achieved by our algorithms.

Original languageEnglish
Pages (from-to)470-484
Number of pages15
JournalLecture Notes in Computer Science
StatePublished - 19 Oct 2005
Event17th International Workshop on Languages and Compilers for High Performance Computing, LCPC 2004 - West Lafayette, IN, United States
Duration: 22 Sep 200424 Sep 2004


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