Power and area reduction in multi-stage addition using operand segmentation

Keyphrases

• Power Reduction 100%
• Area Reduction 100%
• Operand 100%
• Hardware Overhead 50%
• Time Constraints 50%
• Execution Time 50%
• Proposed Architecture 50%
• Power Efficient 50%
• Area-efficient 50%
• FIR Filter 50%
• Timing Margin 50%
• Efficient Hardware Implementation 50%
• Architectural Transformation 50%
• Architectural Techniques 50%

Computer Science

• Hardware Implementation 100%
• Hardware Overhead 100%
• Execution Time 100%
• Critical Path 100%
• Clock Cycle 100%
• Timing Constraint 100%
• Finite Impulse Response Filter 100%

Engineering

• Adders 100%
• Multistage 100%
• Area Reduction 100%
• Clock Cycle 33%
• Execution Time 33%
• Critical Path 33%
• Hardware Overhead 33%
• Architectural Transformation 33%
• Finite Impulse Response Filter 33%