PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Chih Ting Yeh; Ming-Dou Ker

doi:10.1016/j.microrel.2012.09.016

PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Chih Ting Yeh^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

Original language	English
Pages (from-to)	208-214
Number of pages	7
Journal	Microelectronics Reliability
Volume	53
Issue number	2
DOIs	https://doi.org/10.1016/j.microrel.2012.09.016
State	Published - 1 Feb 2013

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10.1016/j.microrel.2012.09.016

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@article{b08e6c0872d5469eaaaddc13d46a005c,

title = "PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit",

abstract = "A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.",

author = "Yeh, {Chih Ting} and Ming-Dou Ker",

year = "2013",

month = feb,

day = "1",

doi = "10.1016/j.microrel.2012.09.016",

language = "English",

volume = "53",

pages = "208--214",

journal = "Microelectronics and Reliability",

issn = "0026-2714",

publisher = "Elsevier Limited",

number = "2",

}

TY - JOUR

T1 - PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

AU - Yeh, Chih Ting

AU - Ker, Ming-Dou

PY - 2013/2/1

Y1 - 2013/2/1

N2 - A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

AB - A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

UR - http://www.scopus.com/inward/record.url?scp=84873720436&partnerID=8YFLogxK

U2 - 10.1016/j.microrel.2012.09.016

DO - 10.1016/j.microrel.2012.09.016

M3 - Article

AN - SCOPUS:84873720436

SN - 0026-2714

VL - 53

SP - 208

EP - 214

JO - Microelectronics and Reliability

JF - Microelectronics and Reliability

IS - 2

ER -

PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

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