Abstract
This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.
Original language | English |
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Pages (from-to) | 1272-1276 |
Number of pages | 5 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 20 |
Issue number | 6 |
DOIs | |
State | Published - Dec 1985 |