Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's

Nicky C.C. Lu; Hu H. Chao; Wei Hwang

doi:10.1109/JSSC.1985.1052468

Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's

Nicky C.C. Lu, Hu H. Chao, Wei Hwang

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.

Original language	English
Pages (from-to)	1272-1276
Number of pages	5
Journal	IEEE Journal of Solid-State Circuits
Volume	20
Issue number	6
DOIs	https://doi.org/10.1109/JSSC.1985.1052468
State	Published - 1 Jan 1985

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title = "Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's",

abstract = "This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.",

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N2 - This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.

AB - This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described.

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Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's

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