Abstract
A new full-adder circuit for pipeline architecture is proposed. Compared with other full-adder circuits, it has high operational speed smallest transistor number and the lowest power/speed ratio. This new full-adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In the MAC, a special pipelined structure is designed to reduce the latency. The whole chip is fabricated in a 0.8 μm Single-Poly-Double-Metal CMOS process and the post-layout simulation of the pipelined 1-bit full adder can work up to 350 MHz. The whole chip which contains 4200 transistor are measured to operate at 125 MHz using 3.3 V power supply.
Original language | English |
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Article number | 5486845 |
Pages (from-to) | 593-596 |
Number of pages | 4 |
Journal | Proceedings of the Custom Integrated Circuits Conference |
Volume | 32 |
Issue number | 1 |
State | Published - 1 Jan 1995 |
Event | Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 1 May 1995 → 4 May 1995 |