Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

Kang Yi Fan; Jyun Hua Chen; Chien Nan Liu; Juinn Dar Huang

doi:10.1109/VLSI-DAT54769.2022.9768095

Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

Kang Yi Fan, Jyun Hua Chen, Chien Nan Liu, Juinn Dar Huang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.

Original language	English
Title of host publication	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665409216
DOIs	https://doi.org/10.1109/VLSI-DAT54769.2022.9768095
State	Published - 2022
Event	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan Duration: 18 Apr 2022 → 21 Apr 2022

Publication series

Name	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference	2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
Country/Territory	Taiwan
City	Hsinchu
Period	18/04/22 → 21/04/22

Keywords

deep learning
ILP
MLP accelerator
performance optimization
weight allocation

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10.1109/VLSI-DAT54769.2022.9768095

Cite this

Fan, K. Y., Chen, J. H., Liu, C. N., & Huang, J. D. (2022). Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. In 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT54769.2022.9768095

Fan, Kang Yi ; Chen, Jyun Hua ; Liu, Chien Nan et al. / Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

@inproceedings{b76c50202b0247a7be17ce07992e324f,

title = "Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy",

abstract = "It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.",

keywords = "deep learning, ILP, MLP accelerator, performance optimization, weight allocation",

author = "Fan, {Kang Yi} and Chen, {Jyun Hua} and Liu, {Chien Nan} and Huang, {Juinn Dar}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 ; Conference date: 18-04-2022 Through 21-04-2022",

year = "2022",

doi = "10.1109/VLSI-DAT54769.2022.9768095",

language = "English",

series = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings",

address = "美國",

}

Fan, KY, Chen, JH, Liu, CN & Huang, JD 2022, Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. in 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, 18/04/22. https://doi.org/10.1109/VLSI-DAT54769.2022.9768095

Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. / Fan, Kang Yi; Chen, Jyun Hua; Liu, Chien Nan et al.
2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

AU - Fan, Kang Yi

AU - Chen, Jyun Hua

AU - Liu, Chien Nan

AU - Huang, Juinn Dar

PY - 2022

Y1 - 2022

N2 - It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.

AB - It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.

KW - deep learning

KW - ILP

KW - MLP accelerator

KW - performance optimization

KW - weight allocation

UR - http://www.scopus.com/inward/record.url?scp=85130429603&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT54769.2022.9768095

DO - 10.1109/VLSI-DAT54769.2022.9768095

M3 - Conference contribution

AN - SCOPUS:85130429603

T3 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

BT - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022

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Fan KY, Chen JH, Liu CN , Huang JD. Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy. In 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings). doi: 10.1109/VLSI-DAT54769.2022.9768095

Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

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