Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

Kang Yi Fan, Jyun Hua Chen, Chien Nan Liu, Juinn Dar Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.

Original languageEnglish
Title of host publication2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665409216
DOIs
StatePublished - 2022
Event2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Hsinchu, Taiwan
Duration: 18 Apr 202221 Apr 2022

Publication series

Name2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings

Conference

Conference2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022
Country/TerritoryTaiwan
CityHsinchu
Period18/04/2221/04/22

Keywords

  • deep learning
  • ILP
  • MLP accelerator
  • performance optimization
  • weight allocation

Fingerprint

Dive into the research topics of 'Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy'. Together they form a unique fingerprint.

Cite this