Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor

Po Chun Huang; Tzu Shiun Sheu; Chen Chia Chen; Lu An Chen; Jeng-Tzong Sheu

doi:10.1109/SNW.2008.5418415

Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor

Po Chun Huang^*, Tzu Shiun Sheu, Chen Chia Chen, Lu An Chen, Jeng-Tzong Sheu

^*Corresponding author for this work

Institute of Nonotechnology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH₃ plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high I_on/I_off current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.

Original language	English
Title of host publication	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs	https://doi.org/10.1109/SNW.2008.5418415
State	Published - 15 Jun 2008
Event	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States Duration: 15 Jun 2008 → 16 Jun 2008

Publication series

Name	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Conference

Conference	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Country/Territory	United States
City	Honolulu, HI
Period	15/06/08 → 16/06/08

Access to Document

10.1109/SNW.2008.5418415

Cite this

@inproceedings{bba80841165d4b0ba3580704ba79f227,

title = "Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor",

abstract = "In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH3 plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high Ion/Ioff current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.",

author = "Huang, {Po Chun} and Sheu, {Tzu Shiun} and Chen, {Chen Chia} and Chen, {Lu An} and Jeng-Tzong Sheu",

year = "2008",

month = jun,

day = "15",

doi = "10.1109/SNW.2008.5418415",

language = "English",

isbn = "9781424420711",

series = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

booktitle = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

note = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 ; Conference date: 15-06-2008 Through 16-06-2008",

}

Huang, PC, Sheu, TS, Chen, CC, Chen, LA & Sheu, J-T 2008, Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor. in IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008., 5418415, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, Honolulu, HI, United States, 15/06/08. https://doi.org/10.1109/SNW.2008.5418415

Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor. / Huang, Po Chun; Sheu, Tzu Shiun; Chen, Chen Chia et al.
IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008. 2008. 5418415 (IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor

AU - Huang, Po Chun

AU - Sheu, Tzu Shiun

AU - Chen, Chen Chia

AU - Chen, Lu An

AU - Sheu, Jeng-Tzong

PY - 2008/6/15

Y1 - 2008/6/15

N2 - In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH3 plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high Ion/Ioff current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.

AB - In this work, performance of dual-channel GAA poly-Si nanowire TFT with NH3 plasma passivation was demonstrated. The proposed devices exhibit low leakage current in off state, a high Ion/Ioff current ratio, a low subthreshold slope, an absence of DIBL and promising output characteristics. It is believed that this high performance poly-Si TFT is suitable for future applications.

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M3 - Conference contribution

AN - SCOPUS:77949963636

SN - 9781424420711

T3 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Y2 - 15 June 2008 through 16 June 2008

ER -

Performance of dual-channel gate-all-around polysilicon nanowire thin-film transistor

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