Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

Chia Chen Lin; Yi Jui Wu; Wei Xiang You; Pin Su

doi:10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

Chia Chen Lin, Yi Jui Wu, Wei Xiang You, Pin Su^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

Original language	English
Title of host publication	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	62-63
Number of pages	2
ISBN (Electronic)	9781728142326
DOIs	https://doi.org/10.1109/VLSI-TSA48913.2020.9203647
State	Published - Aug 2020
Event	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 - Hsinchu, Taiwan Duration: 10 Aug 2020 → 13 Aug 2020

Publication series

Name	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

Conference

Conference	2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020
Country/Territory	Taiwan
City	Hsinchu
Period	10/08/20 → 13/08/20

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10.1109/VLSI-TSA48913.2020.9203647

Cite this

Lin, C. C., Wu, Y. J., You, W. X., & Su, P. (2020). Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 (pp. 62-63). Article 9203647 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA48913.2020.9203647

Lin, Chia Chen ; Wu, Yi Jui ; You, Wei Xiang et al. / Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 62-63 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

@inproceedings{da4815ef25b0410882d639a779a559c7,

title = "Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers",

abstract = "In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).",

author = "Lin, {Chia Chen} and Wu, {Yi Jui} and You, {Wei Xiang} and Pin Su",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-TSA48913.2020.9203647",

language = "English",

series = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "62--63",

booktitle = "2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020",

address = "美國",

}

Lin, CC, Wu, YJ, You, WX & Su, P 2020, Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. in 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020., 9203647, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Institute of Electrical and Electronics Engineers Inc., pp. 62-63, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. / Lin, Chia Chen; Wu, Yi Jui; You, Wei Xiang et al.
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 62-63 9203647 (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

AB - In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

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Lin CC, Wu YJ, You WX, Su P. Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. In 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 62-63. 9203647. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020). doi: 10.1109/VLSI-TSA48913.2020.9203647

Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers

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