TY - GEN
T1 - Performance evaluation of ferroelectric MOSFETs based on Gibbs free energy
AU - Zhang, Xiaoyi
AU - Liang, Gengchiau
N1 - Publisher Copyright:
© 2017 The Japan Society of Applied Physics.
PY - 2017/10/25
Y1 - 2017/10/25
N2 - A comprehensive simulation scheme based on Gibbs free energy calculation is developed to accurately evaluate the device performance of ferroelectric MOSFETs. Its operation region is captured based on the minimum energy point of the whole system involving FE, oxide layer, as well as atomic charge calculation in semiconductor materials. The MOS structure can achieve hysteresis-free mode with negative capacitance effect with both forward and reverse scans. However, for MOSFET structure, the operation region can be affected by different gate lengths of devices and ferroelectric materials. In the selected device, negative capacitance mode can appear with forward scan meanwhile the normal hysteresis effect can appear with reverse scan. This shows hysteresis I-V characteristics and non-symmetric operation loop.
AB - A comprehensive simulation scheme based on Gibbs free energy calculation is developed to accurately evaluate the device performance of ferroelectric MOSFETs. Its operation region is captured based on the minimum energy point of the whole system involving FE, oxide layer, as well as atomic charge calculation in semiconductor materials. The MOS structure can achieve hysteresis-free mode with negative capacitance effect with both forward and reverse scans. However, for MOSFET structure, the operation region can be affected by different gate lengths of devices and ferroelectric materials. In the selected device, negative capacitance mode can appear with forward scan meanwhile the normal hysteresis effect can appear with reverse scan. This shows hysteresis I-V characteristics and non-symmetric operation loop.
KW - 3-D Poisson Solver
KW - Gibbs free energy
KW - Negative capacitance MOSFETs
KW - ferroelectric material
UR - https://www.scopus.com/pages/publications/85039035963
U2 - 10.23919/SISPAD.2017.8085303
DO - 10.23919/SISPAD.2017.8085303
M3 - Conference contribution
AN - SCOPUS:85039035963
T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
SP - 217
EP - 220
BT - 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017
Y2 - 7 September 2017 through 9 September 2017
ER -