TY - GEN
T1 - Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits
AU - Yu, Chang Hung
AU - Su, Pin
AU - Chuang, Ching Te
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/27
Y1 - 2016/5/27
N2 - Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.
AB - Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.
UR - http://www.scopus.com/inward/record.url?scp=84978730215&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2016.7480510
DO - 10.1109/VLSI-TSA.2016.7480510
M3 - Conference contribution
AN - SCOPUS:84978730215
T3 - 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
BT - 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
Y2 - 25 April 2016 through 27 April 2016
ER -