Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits

Chang Hung Yu; Pin Su; Ching Te Chuang

doi:10.1109/VLSI-TSA.2016.7480510

Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits

Chang Hung Yu, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.

Original language	English
Title of host publication	2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394789
DOIs	https://doi.org/10.1109/VLSI-TSA.2016.7480510
State	Published - 27 May 2016
Event	International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016

Conference

Conference	International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

Access to Document

10.1109/VLSI-TSA.2016.7480510

Cite this

Yu, C. H., Su, P., & Chuang, C. T. (2016). Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits. In 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016 Article 7480510 (2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2016.7480510

Yu, Chang Hung ; Su, Pin ; Chuang, Ching Te. / Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits. 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016).

@inproceedings{52e308148c6445fbbcd8097257352116,

title = "Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits",

abstract = "Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.",

author = "Yu, {Chang Hung} and Pin Su and Chuang, {Ching Te}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

year = "2016",

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doi = "10.1109/VLSI-TSA.2016.7480510",

language = "English",

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Yu, CH, Su, P & Chuang, CT 2016, Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits. in 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016., 7480510, 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016, Institute of Electrical and Electronics Engineers Inc., International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-TSA.2016.7480510

Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits. / Yu, Chang Hung; Su, Pin; Chuang, Ching Te.
2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7480510 (2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.

AB - Because of their atomic-scale thickness, adequate band-gap, and pristine interface, monolayer or bilayer two-dimensional transition metal dichalcogenides (TMDs) such as MoS2 and WSe2 (Fig. 1(a)) have emerged as potential channel materials for future ultimately scaled low-power CMOS devices [1-7]. Bilayer TMD devices have been shown to exhibit higher mobility at the expense of device electrostatics compared with monolayer TMD devices [2-6]. While the scalability and performance potential of MoS2 and WSe2 devices have been widely investigated [1-3], a thorough study of the extremely scaled TMD-based logic circuits has been lacking.

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Yu CH, Su P, Chuang CT. Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits. In 2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7480510. (2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016). doi: 10.1109/VLSI-TSA.2016.7480510

Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits

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