Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling dac

Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the rst problem formula-tion in the literature which simultaneously considers capac-itor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consump-tion is minimized while the circuit accuracy/performance is also satised. Experimental results show that the proposed approach can achieve very signicant chip area and power reductions compared with the state of the art.