Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling dac

Po-Hung Lin, Vincent Wei Hao Hsiao, Chun Yu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

20 Scopus citations


Capacitor sizing is a crucial step when designing a charge-scaling digital-to-analog converter. Larger capacitor size can achieve better circuit accuracy and performance due to less impact from random, systematic, and parasitic mismatch. However, it also results in much larger chip area and even more power consumption. In addition to minimizing random and systematic mismatch during common-centroid capacitor placement, this paper presents the rst problem formula-tion in the literature which simultaneously considers capac-itor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consump-tion is minimized while the circuit accuracy/performance is also satised. Experimental results show that the proposed approach can achieve very signicant chip area and power reductions compared with the state of the art.

Original languageEnglish
Title of host publicationDAC 2014 - 51st Design Automation Conference, Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479930173
StatePublished - 1 Jan 2014
Event51st Annual Design Automation Conference, DAC 2014 - San Francisco, CA, United States
Duration: 2 Jun 20145 Jun 2014

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference51st Annual Design Automation Conference, DAC 2014
Country/TerritoryUnited States
CitySan Francisco, CA


  • Capacitor routing
  • Capacitor sizing
  • Parasitic matching


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