Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS

Hao Chiao Hong*, Chien Hung Chen, Yu Wun Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Computing-in-memory (CIM) circuits can energy-efficiently conduct the massive multiply-and-accumulate (MAC) computations required by artificial neural networks (ANNs). However, the CIM's resolution relies on a fundamental assumption of the CIM design: all memory cells output the same current to their read bitlines (RBLs) given the same read wordline voltage and stored weight bit. In practice, parametric faults due to the devices' intrinsic process variations may introduce significant errors to the MAC results. This work implements accurate test circuits with a 4kb read-decoupled 8T (RD8T) SRAM macro in 40nm CMOS to investigate the parametric faults caused by the intrinsic process variations. Our measurement results reveal the detailed spatial distribution of the RD8T cells' output currents and suggest that the CIM accuracy can be improved by calibrating the gain errors of the RBLs.

Original languageEnglish
Title of host publicationProceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350312812
DOIs
StatePublished - 2023
Event7th IEEE International Test Conference in Asia, ITC-Asia 2023 - Matsue, Japan
Duration: 13 Sep 202315 Sep 2023

Publication series

NameProceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

Conference

Conference7th IEEE International Test Conference in Asia, ITC-Asia 2023
Country/TerritoryJapan
CityMatsue
Period13/09/2315/09/23

Keywords

  • analog fault model
  • computing in memory
  • current characterization
  • industry innovation and infrastructure
  • parametric faults

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