Parameterized and low power DSP core for embedded systems

Ya Lan Tsao; Ming Hsuan Tan; Jun Xian Teng; Shyh-Jye Jou

doi:10.1109/ISCAS.2003.1206249

Parameterized and low power DSP core for embedded systems

Ya Lan Tsao^*, Ming Hsuan Tan, Jun Xian Teng, Shyh-Jye Jou

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.

Original language	English
Pages (from-to)	V265-V268
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2003.1206249
State	Published - 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

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10.1109/ISCAS.2003.1206249

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title = "Parameterized and low power DSP core for embedded systems",

abstract = "Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.",

author = "Tsao, {Ya Lan} and Tan, {Ming Hsuan} and Teng, {Jun Xian} and Shyh-Jye Jou",

year = "2003",

doi = "10.1109/ISCAS.2003.1206249",

language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

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T1 - Parameterized and low power DSP core for embedded systems

AU - Tsao, Ya Lan

AU - Tan, Ming Hsuan

AU - Teng, Jun Xian

AU - Jou, Shyh-Jye

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Y1 - 2003

N2 - Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.

AB - Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but also shortens the time-to-market. An Embedded DSP was proposed and for better performance and flexibility we design a parameterized and low power DSP core generator, Dual MAC unit, sub-word multiplier, and some function-specific blocks are adapted to accelerate applications of communication system. The gray code addressing mode, pipeline sharing and advanced hardware looping are designed to reduce power consumption in architecture level. The generator uses graphical user interface (GUI) and can generate synthesizable verilog code of the embedded DSP core according to user's specification.

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U2 - 10.1109/ISCAS.2003.1206249

DO - 10.1109/ISCAS.2003.1206249

M3 - Conference article

AN - SCOPUS:0038420723

SN - 0271-4310

VL - 5

SP - V265-V268

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

Parameterized and low power DSP core for embedded systems

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