Parallel Scrambler for High-Speed Applications

Chih Hsien Lin; Chih Ning Chen; You Jiun Wang; Ju Yuan Hsiac; Shyh-Jye Jou

doi:10.1109/TCSII.2006.875316

Parallel Scrambler for High-Speed Applications

Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiac, Shyh-Jye Jou

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

Original language	English
Pages (from-to)	558-562
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	53
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2006.875316
State	Published - 6 Jul 2006

Keywords

Parallel scrambler
XOR
register

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10.1109/TCSII.2006.875316

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title = "Parallel Scrambler for High-Speed Applications",

abstract = "In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.",

keywords = "Parallel scrambler, XOR, register",

author = "Lin, {Chih Hsien} and Chen, {Chih Ning} and Wang, {You Jiun} and Hsiac, {Ju Yuan} and Shyh-Jye Jou",

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T1 - Parallel Scrambler for High-Speed Applications

AU - Lin, Chih Hsien

AU - Chen, Chih Ning

AU - Wang, You Jiun

AU - Hsiac, Ju Yuan

AU - Jou, Shyh-Jye

PY - 2006/7/6

Y1 - 2006/7/6

N2 - In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

AB - In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scram-bler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

KW - Parallel scrambler

KW - XOR

KW - register

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JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

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ER -

Parallel Scrambler for High-Speed Applications

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Keywords

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