Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation

Tingyou Lin, Chau-Chin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao Chang Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has Ron increased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has Ron increased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.

Original languageEnglish
Title of host publicationProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1661-1666
Number of pages6
ISBN (Electronic)9783981926323
DOIs
StatePublished - 14 May 2019
Event22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy
Duration: 25 Mar 201929 Mar 2019

Publication series

NameProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019

Conference

Conference22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Country/TerritoryItaly
CityFlorence
Period25/03/1929/03/19

Keywords

  • accelerated aging
  • accelerated testing
  • power MOSFET

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