Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

Federico A. Altolaguirre; Ming-Dou Ker

Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

Federico A. Altolaguirre^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.

Original language	English
Title of host publication	2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011
Pages	108-112
Number of pages	5
State	Published - 5 Oct 2011
Event	2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011 - Buenos Aires, Argentina Duration: 6 Aug 2011 → 13 Aug 2011

Publication series

Name	2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011

Conference

Conference	2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011
Country/Territory	Argentina
City	Buenos Aires
Period	6/08/11 → 13/08/11

Cite this

@inproceedings{608bd9a0e5c94d51936baef39fab9dcc,

title = "Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes",

abstract = "The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.",

author = "Altolaguirre, {Federico A.} and Ming-Dou Ker",

year = "2011",

month = oct,

day = "5",

language = "English",

isbn = "9789871620463",

series = "2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011",

pages = "108--112",

booktitle = "2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011",

note = "2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011 ; Conference date: 06-08-2011 Through 13-08-2011",

}

Altolaguirre, FA & Ker, M-D 2011, Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes. in 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011., 6021283, 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011, pp. 108-112, 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011, Buenos Aires, Argentina, 6/08/11.

Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes. / Altolaguirre, Federico A.; Ker, Ming-Dou.
2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011. 2011. p. 108-112 6021283 (2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.

AB - The circuit techniques to overcome the gate leakage issue in advanced nanoscale CMOS technologies are presented. These circuit techniques can reduce the total leakage current from the high value of 21μA in the traditional power-rail ESD clamp circuit down to only 96nA (under 1 Volt operating voltage, at room temperature) while maintaining very high ESD robustness (as high as 8kV HBM and 800V MM) in a 65-nm CMOS technology.

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T3 - 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011

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BT - 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011

T2 - 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2011

Y2 - 6 August 2011 through 13 August 2011

ER -

Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

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